1. Field of the Invention
The present invention relates generally to a method for manufacturing a polycrystalline layer on a substrate, and in particular, to a method for manufacturing a polycrystalline layer of a defined grain size and texture.
2. Description of the Related Art
In semiconductor technology, polycrystalline silicon layers, can be applied in many different ways. Polycrystalline silicon layers are necessary for resistors composed of polycrystalline silicon in integrated circuits, for solar cells, and for silicon-on-Insulator (SOI) technology.
The application of resistances composed of polycrystalline silicon, also known as so-called poly-silicon resistances, on integrated circuits requires reliable realization of the target parameters of the resistances. The parameters are determined by the conditions during deposition, which affect crystallinity and thickness, the implantation dosage or doping agent concentration, and the activation of the doping agent. The implantation dosage and the activation thereby determines the concentration of the chemically dissolved and electrically active doping agents. The selection of deposition conditions determines the crystallinity of the silicon layer. For instance see the references T. I. Kamins, J. Electrochem. Soc., Vol. 127, No. 3, March 1980, pp. 686-690; E. Kinsbron et al, Appl. Phys. Lett. Vol. 42, No. 9, 1 May 1983, pp. 835-837; J. T. McGinn et al, ECS-meeting (May 1983) pp. 647-648; F. S. Becker et al, Appl. Phys. Lett. Vol. 56, No. 4, 15 Aug. 1984, pp. 1233-1236.
One possibility for manufacturing polycrystalline silicon layers is polycrystalline deposition. The grain structure and the texture are determined by the deposition process itself in this case. The following high temperature steps which are in the range of 800.degree. C. to 1050.degree. C. do not significantly alter the crystallinity of the silicon layers. This is particularly true for undoped layers and layers which are doped with boron, for example. On the other hand, phosphorous or arsenic doping results in further grain growth in the polycrystalline layer, however, the reproduceability thereof depends upon the starting conditions of the deposition.
Another possibility for manufacturing polycrystalline silicon layers is that the layer is first deposited in an amorphous mode and is subsequently transformed to a polycrystalline layer via crystallization during a high temperature step. The grain structure and the texture of such layers are determined by the crystallization during the high temperature step. Post-tempering or annealing at low temperatures does not alter the crystallization once the grain structures have been determined. Layers deposited in an amorphous mode which are subsequently crystallized only have approximately 1/3 of the layer resistance of layers that are deposited in a polycrystalline fashion given otherwise equal parameters. For example, see F. S. Becker et al., Appl. Phys. Lett. Vol. 56, No. 4, 15 Aug. 15, 1984, pp. 1233-1236.
Layers deposited in an amorphous mode can thus reach the same target values of resistance with significantly thinner layers. Thus, layers deposited amorphously are an essential means to reduce problems of topography in integrated circuits. One disadvantage, however, of amorphously deposited layers is that extremely great fluctuations in the resulting resistance values of at least .+-.10% result as compared to layers which are deposited in a polycrystalline fashion which have a maximum fluctuation range of .+-.2%.
Therefore, the advantages of amorphously deposited layers can only be used adequately in sub-regions of silicon-micro electronic circuits where precisely adjusted resistant values for the resistance layers are not crucial.
It is known, for example from the reference F. S. Becker et al, Appl. Phys. Lett. Vol. 56, No. 4, 15 Aug. 1984, pp. 1233-1236, that the layer resistance and other electrical features of polycrystalline silicon layers are in correlation with the grain structure and the texture of the layer.